Performance Prediction and Evaluation of Parallel Processing on a NUMA Multiprocessor

Non-Uniform Memory Access (NUMA) architectures make it possible to build large-scale shared memory multiprocessor systems in comparison with non-scalable UniformMemory Access (UMA) architectures. Most NUMA multiprocessor operations such as scheduling and synchronizing processes, accessing data from processors to memory models and allocating distributed memory space to di erent processors, are performed through interconnection networks such as a multistage switching network. The e ciency of these basic operations determines the parallel processing performance on a NUMA multiprocessor. This paper presents several analytical models to predict and evaluate the overhead of interprocessor communication, process scheduling, process synchronization and remote memory access where network contention and memory contention are considered. Performance measurements to support the models and analyses through several numerical examples have been done on the BBN GP1000, a NUMA shared memory multiprocessor. Both analytical and experimental results give a comprehensive and clear understanding of the various e ects, which are important for the e ective use of a NUMA shared memory multiprocessor. The results in this paper may be used to determine optimal strategies in developing an e cient programming environment for a NUMA system. Index Terms | barrier, interprocessor communication, interconnection network, NUMA architectures, pre-scheduling, self-scheduling, remote memory access, shared memory, UMA architectures. This research has been supported in part by the National Science Foundation under grants CCR-9008991 and CCR-9102854, and a grant from the San Antonio Area Foundation, SAAF-26-7400-03.